Sometimes you need to generate a random time value in your testbench. Variable slv : std_logic_vector(len - 1 downto 0) Impure function rand_slv(len : integer) return std_logic_vector is In the code below, the len parameter determines the length of the random std_logic_vector to return. I’m using a for-loop to traverse the vector and select a random value for every bit.
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There are many ways to fill a vector with random values, but this method works with vectors of any length. In the code above, we correct for the endpoint rounding issue by adjusting the random real value to include an additional 0.5 above and below the endpoints. Round(r * real(max_val - min_val + 1) + real(min_val) - 0.5)) Impure function rand_int(min_val, max_val : integer) return integer is Rounding to the 0 integer value happens half of the time, even though there are three number choices. If we base our integer on a random real that goes precisely to the endpoints, the min and max integers only get half the probability of being chosen. In the example, we intend to generate a random integer value in the range -1 to 1. The illustration above shows the problem. You cannot simply generate a random real value within the range and round it to an integer. But there is a pitfall that you have to avoid. To generate a random integer value within a specified range, you have to multiply by a scale and add an offset to it. The code above shows a function that returns a random real value within a min/max range. Return r * (max_val - min_val) + min_val įortunately, we can easily translate the output from uniform by multiplying with a scale and adding an offset to it. Impure function rand_real(min_val, max_val : real) return real is However, the chances are that you want the random number to be on a different range. The real type is VHDL’s floating-point format.
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The uniform procedure generates a random real value between 0.0 and 1.0. The Zip file also contains a ModelSim project with a script that compiles and runs the simulation for you. You can download a complete testbench containing all the examples in this article by using the form below. Then, we implement our custom randomization algorithms as impure functions within the same process. We declare the seed variables as listed below in the declarative region of a process. The test caseĪll of the examples in this article use the value 999 for both seeds. You can also view an actual implementation of the algorithm in the GHDL open-source VHDL simulator. Refer to the Efficient and Portable Combined Random Number Generators paper by Pierre L’Ecuyer for a detailed description of how this algorithm works. Because of this behavior, you can rerun the testbench and get the same result when using the same seed values. Just like other pseudo-random number generators, uniform will generate the same sequence of numbers when called with the same initial seed values. The output, X, is the random number, which always has a value between 0 and 1. It needs two seed variables to work, and it will modify them every time you call the procedure.
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The listing above shows the prototype of the uniform procedure. Procedure UNIFORM(variable SEED1, SEED2 : inout POSITIVE Therefore, none of these algorithms are synthesizable. Please note that uniform relies on software to generate random numbers. The uniform procedure from the IEEE MATH_REAL package is the basis for the algorithms described in this article. Continue reading this article to find out how to produce real or integer values of any range, as well as random std_logic_vector sequences and time values. Fortunately, you can derive from this any other kind of random data format you should need. VHDL has a built-in pseudo-random generator, but it can only generate floating-point numbers between 0 and 1.